
U.S.
Patent
0111.
30,
2001
Sheet
1
of
18
US
6,311,264
B1
F
I
G.
7a
W11
PROG
ADDRESS
/
/
PROG
DATA
1
1
1
1
1
WT
BMAR
MUX 95
1
‘
/
‘
231\
INT
160
CONTROL
'
93/
PC
(16)
l
“
/13
PROGRAM
\101A
STACK‘(816)
V
MEMORY
‘
V
91/
X
1110
\
V
‘1
61
DATA
/
1
81%
11
11
11
1
TREGZ
112501
49\
TRECO
\
MUX
A211
1
1
195
53\
MULTIPLIER
[15
185
-/_1HD
11
11 11
27/’
1
/
\
MUX
A197
PREG
(32)
‘
~ BPR
(32)
S
/
3
V
11
1
0
73A
MUX
/
COUNT
\199
51
"MUX
E
191
_
‘
"
101D/
<
65/
PRESCALER
P_SCALER
\
P
169
g
1
=
ACCB
(32)
~
1
‘7
V
51f
MUX
77
,/
CALL
RET
1A0
[ACK
1
1 1 1
PIPELINE
I’—.>
225/
CONTROLLER
:*
_
ACC
(32)
23
1
Y
POST—SCALER
\181
ALU,MULT---PLU,ARAU---,MUXES
2211
1 1
1
DECODER
PLA
E‘
v
‘
VJ
TO
P10.
111
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